收藏本站
2Gb: x16, x32 Mobile LPDDR2 SDRAM S4
Burst WRITE Command
every eighth clock cycle for BL = 16 operation. This operation is supported as long as the
banks are activated, whether the accesses read the same or different banks.
READs Interrupted by a READ
A burst READ can be interrupted by another READ with a 4-bit burst boundary, provi-
ded that t CCD is met.
A burst READ can be interrupted by other READs on any subsequent clock, provided
that t CCD is met.
Figure 38: READ Burst Interrupt Example – RL = 3, BL = 8, t CCD = 2
T0
T1
T2
T3
T4
T5
T6
T7
T8
CK#
CK
RL = 3
CA[9:0]
Bank n
col addr a
Col addr a
Bank n
col addr b
Col addr b
t CCD
=2
CMD
READ
NOP
READ
NOP
NOP
NOP
NOP
NOP
NOP
DQS#
DQS
DQ
D OUT A0
D OUT A1
D OUT A2
D OUT A3
D OUT B0
D OUT B1
D OUT B2
D OUT B3
D OUT B4
D OUT B5
Transitioning data
Note:
1. READs can only be interrupted by other READs or the BST command.
Burst WRITE Command
The burst WRITE command is initiated with CS# LOW, CA0 HIGH, CA1 LOW, and CA2
LOW at the rising edge of the clock. The command address bus inputs, CA5r–CA6r and
CA1f–CA9f, determine the starting column address for the burst. Write latency (WL) is
defined from the rising edge of the clock on which the WRITE command is issued to the
rising edge of the clock from which the t DQSS delay is measured. The first valid data
must be driven WL × t CK + t DQSS from the rising edge of the clock from which the
WRITE command is issued. The data strobe signal (DQS) must be driven LOW t WPRE
prior to data input. The burst cycle data bits must be applied to the DQ pins t DS prior to
the associated edge of the DQS and held valid until t DH after that edge. Burst data is
sampled on successive edges of the DQS until the 4-, 8-, or 16-bit burst length is com-
pleted. After a burst WRITE operation, t WR must be satisfied before a PRECHARGE
command to the same bank can be issued.
Pin input timings are measured relative to the crosspoint of DQS and its complement,
DQS#.
PDF: 09005aef83f3f2eb
2gb_mobile_lpddr2_s4_g69a.pdf – Rev. N 3/12 EN
62
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2010 Micron Technology, Inc. All rights reserved.
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
MT45W1MW16BDGB-708 AT IC PSRAM 16MBIT 104MHZ 54VFBGA
MT48H32M16LFB4-75B IT:C IC SDRAM 512MB 54VFBGA
MT48H8M16LFB4-75 IT:K TR IC SDRAM 128MBIT 133MHZ 54VFBGA
MTC100-JA2-P34 CONTACT INSERT PIN
MX841BE IC CONVERTER WHITE LED 8-SOIC
MXHV9910BTR IC LED DRIVER HIGH BRIGHT 8-SOIC
MXN12FB12F MOTOR BRUSHED DC 12V 2922RPM
MXN13FB08B1 MOTOR BRUSHED DC 8V 4714RPM
相关代理商/技术参数
MT42L256M32D4KP-MS 制造商:Micron Technology Inc 功能描述:256MX32 LPDDR2 PLASTIC IND TEMP GREEN WFBGA 1.2V - Bulk